1. Field of the Invention
The embodiments of the invention generally relate to integrated circuits, and, more particularly, to complementary metal oxide semiconductor (CMOS) field effect transistors (FETs).
2. Description of the Related Art
Field effect transistors (FETs) are employed in almost every electronic circuit application, such as signal processing, computing, and wireless communications. It is desirable to improve FET performance including the switching speed and on-state current capability. Such an improvement in the performance of FETs stems from enhanced carrier mobility in the FET channel regions. Some conventional techniques deposit epitaxial silicon on relaxed silicon-germanium, which has a larger lattice constant than that of relaxed silicon. However, the presence of the silicon-germanium can cause process issues in the subsequent CMOS fabrication processes, including germanium diffusion into the channels, difficulty in silicide formation, and modified dopant diffusivities, etc. These effects tend to complicate the CMOS fabrication process and generally increase manufacturing cost. Therefore, there remains a need for a technique that increases the charge carrier mobility in the channel regions of FETs, thereby improving the performance of the FETS, and which is compatible with industry accepted FET manufacturing practices and packaging techniques.